RICERCA ITALIANA     

Programmi di ricerca simili:

• 1 - Tecnologie CMOS su scala nanometrica convenzionali (bulk) ed emergenti: una valutazione comparativa dal livello di dispositivo a quello di sistema.
• 2 - Studio degli effetti termofluidodinamici e strutturali per la prevenzione dei rischi negli incendi in galleria Studio dei fenomeni termofluidodinamici e strutturali negli incendi in galleria, per la prevenzione dei rischi e la gestione delle emergenze
• 3 - Sintesi automatica di modelli astratti a partire da dati temporali o spaziali
• 4 - Collegamenti strutturali, discontinuita' fisiche e interfacce materiali: analisi e sperimentazione.
• 5 - Problemi e modelli microstrutturali: applicazioni in ingegneria strutturale e civile
• 6 - Progettazione di nuovi materiali nanostrutturati per applicazioni electroniche ed ottiche attraverso la teoria a principi primi e la simulazione
• 7 - Strategie computazionali integrate per l'interpretazione di proprietà strutturali e dinamiche di sistemi nanostrutturali tramite sonde spettroscopicamente attive.
• 8 - Comprensione ab-initio delle proprieta' strutturali, elettroniche, ottiche di sistemi di semiconduttori nanostrutturati e a bassa dimensionalita'
• 9 - Metodi inferenziali classici e bayesiani in classi di modelli econometrici per la finanza
• 10 - Analisi e simulazione di modelli dinamici con aspettative eterogenee

Classificazione scientifico-disciplinare

• Area scientifico disciplinare: Ingegneria industriale e dell'informazione
  • ELETTRONICA

Classificazione brevettuale

• ELECTRICITY
  • BASIC ELECTRIC ELEMENTS
    • SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR (use of semiconductor devices for measuring G01; details of scanning-probe apparatus, in general G12B21/00; resistors in general H01C; magnets, inductors, transformers H01F; capacitors in general H01G; electrolytic devices H01G9/00; batteries, accumulators H01M; waveguides, resonators or lines of the waveguide type H01P; line connectors, current collectors H01R; stimulated emission devices H01S; electromechanical resonators H03H; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers H04R; electric light sources in general H05B; printed circuits, hybrid circuits, casings or constructional details of electric apparatus, manufacture of assemblages of electrical components H05K; use of semiconductor devices in circuits having a particular application, see the subclass for the application) [C0103]

Classificazione geografica

• Regione: Toscana

Bibliografia

[1] International Technology Roadmap for Semiconductors 2003, Semiconductor Industry Association, S. Josè, USA (http://public.itrs.net)
[2] G. Baccarani et al., "Generalized Scaling Theory and Its Application to a 1/4 Micrometer MOSFET Design",IEEE-TED, vol.ED-31, 1984, p.452.
[3] J.R. Brews, "The submicron MOSFET", in "High speed semiconductor devices", John Wiley, 1990.
[4] S.Takagi et al., IEEE-TED, "On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration" vol.ED-41, 1994, p.2357.
[5] A.Asenov et al., "Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study" IEEE-TED, vol.ED-48, 2001, p.722.
[6] C.Fiegna et al. IEEE-TED, "Scaling the MOS transistor below 0.1 um: methodology, device structures, and technology requirements", vol.ED-41, June 1994, p. 941
[7] E. Suzuki et al., "Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs" IEEE-TED, vol.ED-47, 2000, p.354
[8] M.Jurczak et al., "Silicon-on-Nothing (SON)-an innovative process for advanced CMOS" IEEE-TED, vol.ED-47, 2000, p.2179.
[9] R. H. Dennard et al., "Design of ion-implanted MOSFET's with very small physical dimensions" IEEE-JSSC, vol. SC-9, 1974, p.256.
[10] A. Kawamoto et al., "Challenges for atomic scale modeling in alternative gate stack engineering", IEEE Trans. Electron Devices Vol. 47 2000, pp. 1787-1794.
[11] See for example Finnis M W (ed) 2002 Special issue on atomistic modelling of solids 2002 J. Phys.: Condens. Matter 14 11
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[19] D.Esseni et al.,"Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application ", IEEE-TED, vol. 48, no.12, 2001, pg.2842.
[20] D.Esseni et al.,"An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode" EEE-TED, vol. 50, no.3, 2003, p.802.
[21] K.Uchida et al.,"Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm", IEDM Techn.Digest, 2002, p.47.
[22] K.Uchida et al.,"Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering", IEDM Techn.Digest, 2003, p.805.
[23] F.Gamiz et al. "Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFET's", IEEE-TED, vol.45,no5, 1998, p.1122.
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Journal of Applied Physics, vol. 85, no 5, 1999, p.2722.
[25] M.Lundstrom, "Device physics at the scaling limit: what matters?", IEDM Techn.Digest, 2003, p.789.
[26] D. Wang et al., "Germanium nanowire field-effect transistors with SiO2 and high- kHfO2
gate dielectrics", Appl. Phys. Lett. vol. 83, 2003, pp. 2432-2434.
[27] S.-W. Chung et al.,"Silicon nanowire devices", Appl. Phys. Lett. vol. 76, 2000, pp. 2068-2070
[28] S. Miyano et al., "Numerical Analysis of a Cylindrical Thin-Pillar Transistor (CYNTHIA)", IEEE Transaction on Electron Devices, 39(8), 1992, p.1876.
[29] Y. Taur,"An Analytical Solution to a Double-Gate MOSFET with Undoped Body", IEEE Electron Device Letters, 21(5), 2000, p.245.
[30] E. Pokatilov et al.,"Distribution of Field and Charge in Cylindrical Nanosize Silicon-based Metal-oxide-semiconductor Structures", Journal of Applied Physics, 85(9), 1999, p.6625.
[31] A. Pacelli,"Self-consistent Solution of the Schroedinger Equation in Semiconductor Devices by Implicit Iteration",
IEEE Transaction on Electron Devices, 44(7), 1997, p.1169.
[32] M. G. Ancona et al.,"Density-gradient analysis of MOS tunneling", IEEE Trans. Electron Devices Vol. 47, 2000, pp. 2310-2319.
[33] A. Burenkov et al.,"Corner effect in double and triple gate FinFETs", IEDM 2003,pp. 135-138.
[34] A. Spinelli et al.,"Self-consistent 2D model for quantum effects in nMOS transistors", IEEE Trans. Electron Devices Vol. 45, 1998, pp.1342-1349
[35] A. Abramo et al.,"Two-dimensional quantum mechanical simulation of charge distribution in silicon MOSFETs", IEEE Trans. Electron Devices Vol. 47, 2000, pp. 1858-1863.
[36] A. Pirovano et al.,"Two-dimensional quantum effects in nanoscale MOSFETs", IEEE Trans. Electron Devices Vol. 47, 2002, pp. 25-31.
[37] G. Fiori et al.,"Modeling of ballistic nanoscale metal-oxide-semiconductor field effect transistor", Appl. Phys. Lett. Vol. 81, 2002, pp.3672-3674.
[38] Z. Ren et al.,"The ballistic nanotransistor: a simulation study", IEDM Tech. Dig., 2000, pp. 715-718.
[39] A. Svizhenko et al.,"Two-dimensional quantum mechanical modeling of nanotransistors", J. Appl. Phys., Vol. 91, 2000, pp. 2343-2354.
[40] Complete information and manuals available at http://www-device.eecs.berkeley.edu/~bsim3/bsim_ent.html,
[41] M. Miura-Mattausch, et al., "HiSIM: A MOSFET Model for circuit simulation connecting circuit performance with technology", IEDM Tech. Dig. 2002, 2000, pp. 109-112.
[42] C. C. Enz et al.,"An analytical MOS transistor model valid in all regions of operations and dedicated to low-voltage and low-current applications", Analog Integrated Circuits and Signal Processing, Vol. 8, 1995, pp. 83-114.
[43] A. I. A. Cunha et al.,"An MOS transistor model for analog circuit design", IEEE J. Solid-State Circuits, Vol. 33, 1998, pp.1510-1519.
[44] H. K. Gummel et al.,"Inversion Charge Modeling", IEEE Trans. Electron Devices, Vol. 48, 2001, pp. 1585-1593.
[45] J. G. Fossum et al.,"A process/physics-based compact model for nonclassical CMOS device and circuit design", Solid-State Electronics, Volume 48, Issue 6, June 2004, pp. 919-926
[46] D.B.M.Klaassen et al.,"The MOS model, level 1101, Philips Research Laboratories"
[47] G.Gildenblat et al.,"SP: An advanced Surface-Potential-Based Compact MOSFET Model",IEEE Custom Intergrated Circuits Conference, 2003
[48] G. Baccarani et al.,"A compact Double-Gate MOSFET model comprising quantum-mechanical and nonstatic effects", IEEE Trans. Electron Devices, Vol. 46, 1999, pp. 1656-1666.
[49] P. Francis et al.,"Modeling of ultrathin doublegate nMOS/SOI transistors", IEEE Trans. Electron Devices, Vol. 41, 1994, pp. 715-720
[50] A. Rahman et al.," A compact scattering model for the nanoscale double-gate MOSFET", IEEE Trans. Electron Devices, Vol. 49, 2002, pp 481-490.
[51] F. G. Pikus et al.,"Nanoscale field-effect transistors: An ultimate size analysis", Appl. Phys. Lett. Vol. 71, 1997, pp. 3661-3663.
[52] Y. Naveh et al.,"Modeling of 10-nm-scale ballistic MOSFET's", IEEE Electron Device Letters, Vol. 21, 2000, pp. 242-244.

Parole Chiave

ITRS; NANOMOSFET; TCAD; ELETTRONICA DELLO STATO SOLIDO